SPI FIFO global control register. These registers are byte, halfword, and word addressable. The upper 16 bits of these registers provide information about the System FIFO configuration, and are specific to each device type.
| RXPAUSE | Pause all SPIs receive FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI receivers. |
| RXPAUSED | All SPI receive FIFOs are paused. |
| RXEMPTY | All SPI receive FIFOs are empty. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| TXPAUSE | Pause all SPIs transmit FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI transmitters. |
| TXPAUSED | All SPI transmit FIFOs are paused. |
| TXEMPTY | All SPI transmit FIFOs are empty. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXFIFOTOTAL | Reports the receive FIFO space available for SPIs on the System FIFO. The reset value is device specific. |
| TXFIFOTOTAL | Reports the transmit FIFO space available for SPIs on the System FIFO. The reset value is device specific. |